As a semiconductor memory device provided with a film bypass capacitor, a technique disclosed in Patent Document 1 has been known, for example. In Patent Document 1, a memory chip includes center pads, where the center pads and substrate wiring formed on a surface of the substrate on the opposite side to the mounting surface are connected by wire bonding via an opening portion formed on the mounting substrate. In this connection structure of the memory chip, thin-film decoupling capacitors (thin-film bypass capacitors) are formed in a region adjacent to the memory chip. Thus, Patent Document 1 discloses a technique that aims at minimizing the parasitic inductance due to electrode structure by forming the thin-film bypass capacitors in the region adjacent to the memory chip.
Patent Document 1: Japanese Unexamined Patent Publication No. 2009-55040
In recent years, however, the clock frequency of semiconductor memory devices is as high as 400 MHz or higher, and the data bit width is also increased. As a result, there are increasing demands for the stability of a power supply voltage and the noise reduction during multi-bit I/O interface in a semiconductor memory device.
In the memory chip including the center pads, the center pads and an external circuit are connected by wire bonding via the opening portion on the mounting substrate. In the case of the bypass capacitors (on the order of the parasitic capacity between electrodes), at the periphery of the opening portion, including a thin-film layer of an amorphous metal oxide film formed on one side of an organic substrate constituting a package, the density of capacitance that can be formed on the organic substrate is extremely low. Accordingly, when the memory performs a multi-bit write or read at high speed, a problem arises that required charges cannot be sufficiently supplied at a close distance.
In the present description, there is disclosed a semiconductor memory device with a memory chip including a center pad, the semiconductor memory device improving an effect of reducing the power supply noise in a high-frequency interface and eliminating the need for an opening portion for external connection on a substrate on which a memory chip is mounted.